The process of placement, which involves determining the spatial coordinates of numerous standard cells and macros, is a critical and labor-intensive stage in contemporary Very Large-Scale Integration (VLSI) physical DESIGN. The placement of components in a circuit has long been challenging due to the increasing complexity of structures and the continuous advancements in VLSI manufacturing techniques. This research introduces a Reinforcement Learning (RL) strategy known as the Reinforcement Learning Parameter Optimization Model (RLPOM) and a Graph Neural Network (GNN) to formulate the parameter optimization problem as a RL task. The agent is trained exclusively using RL through a self-search approach. The selection of the RL algorithm is motivated by the need to address the challenges posed by data sparsity and latency in placement runs. The mean outcomes of the proposed RLPOM across all performance measures are as follows: The measured parameters for the system under study include wire length (13. 71 um), congestion (4. 5%), area utilization (82. 4%), run time (26. 68 sec), power consumption (15. 57 W). This approach leverages the natural advantages of GNN and RL to achieve superior global placement, which is unique to the best of our knowledge.

Digital transformers are considered as one of the digital circuits being widely used in signal and data processing systems, audio and video processing, medical signal processing as well as telecommunication systems. Transforms such as Discrete Cosine Transform (DCT), Discrete Wavelet Transform (DWT) and Fast Fourier Transform (FFT) are among the ones being commonly used in this area. As an illustration, the DCT is employed in compressing the images. Moreover, the FFT can be utilized in separating the signal spectrum in signal processing systems as fast as possible. The DWT is used in separating the signal spectrum in a variety of applications from signal processing to telecommunication systems, as well. In order to build a VLSI circuit, several steps have to be taken from chip DESIGN to final construction. The first step in the synthesis of the integrated circuits is called high-level synthesis (HLS), in which a structural characteristic is obtained from a behavioral or algorithmic description. The resulting structural characteristic is equivalent to the one being considered in the behavioral description and it somehow represents the method for implementing the behavioral description as a result several structural descriptions could be implementable for each behavioral description. Therefore, depending on the intended use, the characteristic will be selected that outperforms the others. The main purpose of the HLS is to optimize the power consumption, the chip occupied area and delayed and is fulfilled by selecting the appropriate number of operating units and how they are implemented to the operators. This is generally accomplished through a graph analysis called the data flow graph (DFG) which is a graphical representation of the type and how the operators connect. In the DFG, each node is equivalent to an operator while the edges represent the relationship between these operators. Experience has proved that if the level of DESIGN optimization is high, in addition to higher efficiency, the DESIGN time will be lower, which is why the researchers are far more interested in optimization at higher levels of DESIGN than the lower levels. The complex, extensive, and discrete nature of the HLS problems have been ranked them among the most complex problems in VLSI circuits engineering. Bearing this mind, using meta-heuristic and Swarm intelligence methods to solve high-level synthesis projects seems to be a favored option. In this paper, a heuristic method called Moth-Flame Optimization (MFO) has been used to solve the HLS problem in the DESIGN of digital transformer to find the optimal response. The MFO is a population-based heuristic algorithm that optimizes the problems using the laws of nature. The leading notion behind the MFO algorithm inspired from the moths’ movements and their instinctive navigation during the night. In the MFO algorithm, the moths are like chromosomes in the GA and like the particles in the PSO algorithm. In order to compare and prove the efficiency of the proposed method, it was applied on the test data with the GA-based method separately but with the same initial conditions. The comparative results along with the results of the GA-based method demonstrated that the proposed method exhibits a higher ability to provide the appropriate hardware structure and high-level synthesis of various types of transformers. Another outstanding feature of the proposed method is its high speed of finding an optimal response with an average of more than 20% greater than the GA based method.

This paper proposes the efficient VLSI architecture of camera distortion correction, based on a Neural Camera Distortion Model (NCDM). Conventional imaging methods use over two kinds of models to correct the camera and lens distortions, but the NCDM uses a single model to immediately correct the geometry distortion and unsymmetrical manufacturing errors. The NCDM, with four neurons, performs a wide-angle distortion correction. The results show that the maximal corrected error in a whole image is less than 1.1705 pixels, and the MSE approaches 0.1743 between corrected and ideal results. The distortion correction by NCDM is 429more accurate than the conventional approach. The chip size of NCDM is 1: 51×1: 51 mm2 and contains 126 K gates using the TSMC 90 nm CMOS technology process. Working at 240 Mhz, this architecture can correct 30 frames and a Full-HD resolution video per second. Results show that the maximal corrected error in a whole image is less than 1.4 pixels, and the mean square error approaches 0.0376 between corrected and ideal results.

With the growing complexity of VLSI systems, automatic physical DESIGN of today's systems has become very complex. One approach to control overall complexity is to divide the DESIGN into several levels of hierarchy. This may produce poor results if the inter-dependence between various components of the DESIGN is not considered. In addition, the high degree of inter-dependence between DESIGN processes operating at the physical and higher levels of abstraction (e.g. the specification level) necessitates a number of iterations between these levels. One effective solution, exploited by this work, is the use of a common DESIGN hierarchy for both specification and physical level DESIGN. This can provide physical data to the specification level synthesis process, thereby reducing the DESIGN cycle. In this paper, a framework for the floorplanning and placement of macrocell DESIGNs is introduced. Inter-dependence between levels of a DESIGN specification hierarchy is taken into account in this framework. Since the framework is not inherently restricted by either the hierarchy depth or the hierarchy branching factor, it is able to preserve an arbitrary specification hierarchy. The framework gathers geometric information about the DESIGN over several traversals of the DESIGN specification hierarchy and sets the physical geometries, such as port positions, orientation, etc., in a stepwise refinement fashion. The results show that the framework produces good results quickly for large DESIGNs.  

Intracytoplasmic sperm injection (ICSI) is one of the most successful techniques of Assisted Reproductive Technology (ART) and is mostly in use for the treatment of infertility with male factors. In this method, before injecting sperm into the intracytoplasmic of the oocyte, cumulus cells around the oocyte must be stripped to facilitate the injection process. To achieve this, both enzymatic and mechanical methods are used in embryological laboratories for denudation, which has major deficiencies, including the possibility of damaging the oocyte prior to the injection process. In this research, a microfluidic-based device is introduced for the separation of cumulus cells around the oocyte with minimum manual operations. The results prove high efficiency, and non-destructive denudation of the oocyte with the reduced amount of culture medium leads to the low-cost preparation process of oocytes. The process can also be integrated with ICSI chips under development and will be reported shortly.

Image data require huge amounts of disk space and large bandwidths for transmission. Hence, image compression is necessary to reduce the amount of data required to represent a digital image. Therefore an efficient technique for image compression is highly pushed to demand. Although, lots of compression techniques are available, but the technique which is faster, memory efficient and simple, surely hits the user requirements. In this paper, the image compression, need of compression, its principles, how image data can be compressed, and the image compression techniques are reviewed and discussed. Also, wavelet-based image compression algorithm using Discrete Wavelet Transform (DWT) based on B-spline factorization technique is discussed in detail. Based on the review, some general ideas to choose the best compression algorithm for an image are recommended. Finally, applications and future scopes of image compression techniques are discussed considering its development on FPGA systems.